The present invention generally relates to a soft metal conductor for use in a semiconductor device and a method of making such conductor and more particularly, relates to a soft metal conductor that has improved wear resistance in its surface layer for use in a semiconductor device wherein the surface layer consists of metal grains having grain sizes sufficiently large so as to provide a substantially scratch-free surface upon polishing in a subsequent chemical mechanical polishing step and a dual-step deposition method for making such conductor.
Metal films have been utilized in semiconductor manufacturing to electrically connect together various components formed on a semiconductor wafer. For instance, vias, interconnects, trenches are just a few examples of such applications. Elemental aluminum and its alloys such as aluminum-copper have been used traditionally for these applications. The advantages of using aluminum and its alloys include the low resistivity, the superior adhesion to SiO2, the ease of patterning, the high purity and low cost of the materials.
Aluminum and aluminum alloys are not without drawbacks when utilized in semiconductor technology. Two of these drawbacks are the softness of the materials which results in difficulty in polishing and the electromigration phenomenon which results in circuit failure. For instance, the polishing problem has been observed in a process where metal films or metal conductive lines are formed in a damascene process by first filling troughs previously etched in an insulator with a metal and then polishing away metal deposited between the troughs. When a soft metal is used, i.e., aluminum, copper or aluminum-copper alloy, the surface of the metal lines may become scratched in a polishing process. The formation of defects during polishing of scratches, pockets, depressions or erosions in the metal surface significantly increases the line resistance and thus reduces the yield of the semiconductor manufacturing process.
In order to avoid these defects produced in the polishing process of soft metals, capping by hard layers has been tried by others to improve the wear resistance of the surface layer of the metal. However, this is achieved at the expense of higher capacitance as the line thickness increases. It is inherently difficult to improve the wear resistance of soft metals which requires the processing steps of polishing. Poor polishing results in variations in the line or via resistance.
It is therefore an object of the present invention to provide a soft metal conductor that has improved wear resistance in its uppermost surface and a method of making the same without the shortcomings of the prior art conductors and the prior art methods.
It is another object of the present invention to provide a soft metal conductor that has improved wear resistance in its uppermost surface such that a substantially scratch-free surface can be obtained after polishing in a chemical mechanical polishing process.
It is a further object of the present invention to provide a soft metal conductor that has improved wear resistance in its uppermost surface by simply modifying the processing conditions of the deposition process for the soft metal.
It is yet another object of the present invention to provide a soft metal conductor that has a substantially scratch-free surface upon polishing by depositing a soft metal layer consisting of metal grains having large grain sizes in its uppermost layer.
It is another further object of the present invention to provide an electrically conducting soft metal structure that has a substantially scratch-free surface upon polishing by depositing in the uppermost layer of said structure grains of soft metal not smaller than about 200 nm.
It is still another object of the present invention to provide an electrically conducting soft metal structure that has a substantially scratch-free surface upon polishing for use in a semiconductor device by depositing in the uppermost layer of said structure metal grains having grain sizes not smaller than about 20% of the thickness of the soft metal structure.
It is still another further object of the present invention to provide an electrically conducting soft metal structure that has a substantially scratch-free surface upon polishing for use in a semiconductor device wherein the surface has a layer of at least about 100 nm in thickness of large grain size metal grains deposited therein.
It is yet another further object of the present invention to provide a method of making a soft meal conductor that has a substantially scratch-free surface upon polishing for use in a semiconductor device by a physical vapor deposition technique, a chemical vapor deposition technique or a dual-step deposition technique.
During chem-mech polishing (CMP), overall wear resistance is important. Wear could be due to the combination of chemical and mechanical action and the contribution of each is difficult to separate. It has been experimentally observed in by the inventors that the large grains during the high temperature deposition process or thermal annealing or combination of low temperature deposition followed by high temperature annealing or deposition improves wear resistance. These facts can be technically explained as follows: A. During CMP,xe2x80x9cwearxe2x80x9d mechanisms can be attributed to chemical wear in combination with adhesion, abrasion and delamination wear. It appears that these components attack the large grains differently.
For mechanical component strength, adhesion (if loose debris are formed they can scratch the metallic layers), hardness etc. are important. For chemical component etchability in the chemical solution, slurry composition (pH), microstructure, etc., play a role in metal removal. Other parameters such as polishing pressure, speed, and pad structure play a significant role. Keeping other parameters constant, large grains with minimal defects may resist overall wear better than the small grains. It can be deduced that the ratio of atoms on the grain boundary and atoms in the grain itself =2xc3x9710xe2x88x923/(xd), where x is lattice spacing and d is grain size in microns, assuming a square grain). Thus the larger the grain size smaller is the fraction of atoms on the grain boundary for constant x. Also, smaller grains (having larger surface of grain boundaries) are prone to chemical attack during CMP. Once the grain are loose they can be easily knocked down due to mechanical action during CMP. These debris can scratch the metal. Thus it is possible that small grains can wear faster than large grains. Experimental results support this statement.
In addition, small grains when annealed to form large grains or large grains formed at high temperature deposition process reduces the free volume or defect structure changing the grain boundary (free volume or defects are susceptible to chemical attack). The reduction of these defects during grain growth may improve resistance to chemical attack at the grain boundaries and also improve wear related to adhesion.
B. If impurities are added in the film they would segregate at grain boundaries during grain growth. In the case of alloys (e.g Alxe2x80x94Cu), intermetallic would form at the grain boundaries. These impurities or intermetallic can prevent attack at the grain boundaries or improve wear resistance during CMP. Impurities which impart sufficient wear resistance would be beneficial from the point of view of CMP. In short large grains formed by thermal annealing or high temperature deposition or combination, etc., would improve wear resistance (also improvement of adhesion, less debris during polishing and scratching) based on the reasons given above.
In accordance with the present invention, a soft metal conductor that has a substantially scratch-free uppermost surface upon polishing for use in a semiconductor device and a method of making the same is provided.
In the preferred embodiment, the soft metal conductor is provided by depositing an uppermost layer of the conductor consisting of grains having grain sizes not smaller than about 20% of the thickness of the soft metal conductor. This is achieved by, for instance, depositing an uppermost layer of the soft metal material to a thickness of not less than 100 nm with grains of soft metal not less than 200 nm in grain sizes. The large grains provide a significantly improved wear resistance in the uppermost layer of the soft metal conductor such that a substantially scratch-free surface upon polishing in a subsequent chemical mechanical polishing process is obtained. By substantially scratch-free, it is meant that a surface is obtained after polishing that has less than five scratches per square centimeter area.
In an alternate embodiment, a layer of soft metal having smaller grains, i.e., a grain size of not larger than 50 nm is first deposited in the soft metal conductor to a thickness of not less than 600 nm, an uppermost layer of large grains having grain sizes not smaller than 200 nm is then deposited on top of the layer of small grains. The large grain size in the uppermost layer provides the desirable scratch-free surface for polishing, while the middle layer of soft metal in small grains provides a layer of material without the thermal voiding problem.
In another alternate embodiment, a layer of soft metal having small grains of less than 50 nm in size is sandwiched between a bottom layer and a top layer of metal consisting of grains of larger than 200 nm in size.
In yet another alternate embodiment, after a large grain soft metal M1 is deposited, a layer of Ti (or Ti/TiN) is sequentially deposited on top of the soft metal. The Ti layer (or Ti/TiN) deposited at the interface between the via and M1, M2 has a thickness of not higher than 30 nm so as to provide improved anti-electromigration property in the soft metal conductor after the Ti layer is converted to a TiAl3 layer in a subsequently conducted annealing process at 400xc2x0 C. M1, M2 are metal stacks of Ti/Alxe2x80x94Cu/Ti/TiN.
The present invention is also directed to a method of making a soft metal conductor that has a substantially scratch-free surface upon polishing by a multi-step deposition process, i.e., first sputtering at 450xc2x0 C. for 10-15 sec, then at 400xc2x0 C. for 2 min and followed by 450xc2x0 C. for 15-20 sec. A soft metal conductor that has improved wear resistance in its uppermost surface can be obtained.
The present invention is further directed to a method of forming a substantially scratch-free surface on a soft metal conductor by first depositing a soft metal layer at a low deposition temperature and then annealing the soft metal layer at a higher temperature to increase the grain size of the metal.
The present invention is further directed to a method for making a soft metal conductor for use in an electronic device that can be carried out by the steps of first depositing a first layer of metal by a physical vapor deposition technique to a first thickness, and then depositing a second layer of metal on top of the first layer of metal to a second thickness larger than the first thickness by a method such as chemical vapor deposition, electroplating or electroless plating. The first and the second metal layer can be deposited of a metal such as Al, Cu, Ag, AlCu, CuAg, AlAg and AlCuAg. The second metal layer deposited has an average grain size of not smaller than 0.3 xcexcm. The first thickness of the first layer of metal is at least 200 nm (nominal 100 nm), while the second thickness of the second layer of metal is at least 300 nm. The second layer of metal can be deposited by a chemical vapor deposition technique at a reaction temperature of not less than 300xc2x0 C. The first layer of metal can be deposited by a physical vapor deposition technique that includes large grain copper alloyed with an element such as C, B, N, or elements selected from Group IIIA, IVA and VA for improved wear and electromigration resistance. The second layer of metal deposited has a sheet resistance of not higher than 0.1 xcexa9/xe2x96xa1.
The present invention is further directed to a dual-step deposition method for making a soft metal conductor for use in an electronic device that includes the steps of first depositing a first layer of metal by a chemical vapor deposition technique to a first thickness, and then depositing a second layer of metal by a technique such as electroplating, electroless plating or high temperature physical vapor deposition to a second thickness. The first metal layer deposited has an average grain size of not smaller than 0.1 xcexcm. The first layer of metal can be deposited by a chemical vapor deposition technique resulting in a sheet resistance not higher than 0.1 xcexa9/xe2x96xa1.
The present invention is still further directed to a method for forming an interconnect in a logic or memory device by at least two levels of metal which can be carried out by the operating steps of first depositing at least one layer of metal into a line or via hole of Cu, Ag, Al and binary and ternary alloys thereof, and then depositing a final layer of Cu which has an average grain size of not smaller than 0.3 xcexcm on top of the at least one layer of metal into the line or via hole. The at least one layer of metal may include two layers of metal deposited into a line or via hole. The final layer of Cu has a sheet resistance of not more than 0.1 xcexa9/xe2x96xa1.
The present invention is further directed to a method for forming an interconnect structure that is surrounded at least on 3 sides by an amorphous barrier layer which can be carried out by the steps of first depositing an amorphous barrier layer of refractory metal nitride or carbide into a line or via hole by a vapor deposition technique, and then depositing a layer of a conductive metal which has an average grain size of not smaller than 0.3 xcexcm on top of the amorphous barrier layer to fill the liner or via hole. The amorphous barriers includes refractory metal in the refractory metal nitride barriers or carbides or borides of W, Ta or Ti alloyed with Si. The conductive metal can be deposited at a temperature between about 300xc2x0 C. and about 400xc2x0 C. The refractory metal nitride can be deposited by a sputtering technique by using a composite target of metal and silicon in nitrogen ambient. The method may further include the step of annealing the amorphous barrier layer at a temperature of not lower than 400xc2x0 C. for at least a half hour prior to the conductive metal deposition step. The method may further include embedding the interconnect structure formed by the amorphous barrier layer and the conductive metal. The hard dielectric layer may be deposited of a material of either a fluorinated oxide or a fluorinated nitride.